The invention relates generally to input/output circuits and, more particularly, to an input driver circuit having the capability to accept multiple input voltage standards.
Integrated circuits (ICs) typically include numerous transistors that are fabricated on, for example, silicon wafers. To increase production yields and lower total IC device costs, semiconductor manufacturers are continually striving to reduce the size of the transistors in IC devices. However, for a given power supply voltage, the electric field strength, e.g., the change in voltage per unit length, that these transistors are exposed to increases as the size of the transistors is reduced. As IC device geometries shrink to the deep sub-micron level (i.e., less than 0.5 um), the electric fields generated by the 5V supply voltages historically used to power IC devices can degrade or even destroy the transistors in those IC devices. For example, the performance of a sub-micron MOS transistor having an effective channel length of 0.35 um is impaired under a 5V supply voltage due to injection of hot electrons into the gate of the MOS transistor. In addition, the electric field generated by a 5V supply voltage across a submicron MOS transistor can also cause total failure due to gate oxide breakdown. Therefore, a reduced power supply voltage must be available to reap the cost and efficiency benefits of deep sub-micron transistors while maintaining overall IC performance and reliability. Recent trends toward the use of 3.3V and lower supply voltages is indicative of this need, and further reductions in supply voltages will become necessary as IC device geometries continue to shrink.
At the same time, a 3.3V external supply voltage will not necessarily be available to power deep sub-micron IC devices. While memory and microprocessor boards can often be custom designed to provide 3.3V to those IC devices, other types of IC devices may not have that option available. For example, Programmable Logic Devices (PLDS) are a type of IC device comprising user-configurable logic elements and interconnect resources that are programmable to implement user-defined logic operations (that is, a user""s circuit design). PLDs have begun to incorporate 0.18 um transistors that require a 1.8V power supply voltage. However, because of their configurable purpose, PLDs will often be used in systems that operate under many different power supply voltages due to other IC devices in the system that require, for example, LVCMOS and LVTTL input/output (I/O) standards (e.g., 5V, 3.3V, 2.5V, 1.5V, etc.).
An approach compensating for these differing (I/O) voltage standards is to utilize a double-inverter circuit. The double-inverter circuit has an input inverter and an output inverter serially coupled together. The input inverter circuit accepts a signal according to its particular (I/O) voltage standard and outputs an inverted signal according to the same voltage standard to the output inverter circuit. The output inverter circuit accepts this signal and outputs an inverted signal according to the (I/O) standard of the circuitry down stream of the double-inverter circuit. Typically, the output inverter circuit steps down the signal level to the internal power supply voltage of the down stream circuitry. This method has numerous disadvantages. One disadvantage is that the input inverter circuitry must be designed according to the usually higher voltage requirements of the input signal""s (I/O) standard. This means that the circuitry usually requires more silicon in an IC to implement than lower voltage circuits. Hence, it takes up more room on an IC chip and, therefore, makes the IC chip physically larger. Moreover, because the input inverter circuitry is larger and designed to work with higher voltage standards, it usually has higher threshold voltages that contribute to slower operation than circuitry designed to work with lower voltage standards. Still further, the input inverter circuitry usually derives its switching characteristic from the external power supply forming the basis of the higher input signal voltage standard. Hence, any noise present in the external power supply voltage necessarily tends to permeate through the input inverter circuitry and on through the output inverter circuitry. Such a condition can cause false outputs by the output inverter circuitry.
Hence, a system and method for safely managing varying I/O signal standards that does not suffer from the above-mentioned disadvantages is highly desirable.
According to one embodiment of the present invention, an input driver circuit for accommodating a plurality of input/output voltage standards is provided. The input driver circuit employs an adjustable trip point that can be calibrated for multiple input voltage standards. The input driver circuit has, for example, an inverter circuit in circuit communication with a signal input and has an output. The input driver circuit further has a trigger circuit cooperating with the signal input and the inverter circuit. A control circuit cooperates with the trigger circuit to determine whether the trigger circuit should be on or off by comparing a configuration input and a reference power supply input. Depending on whether a voltage at the reference supply input is greater or less than a voltage at the configuration input, the control circuit turns on and off the trigger circuit. When the trigger circuit is on, it has a trip point that is active during a low to high transition of the signal input.
Hence, it is an advantage of the present invention to provide an input driver circuit for multiple input signal voltage standards.
It is another advantage of the present invention to provide an input driver circuit having an adjustable trip point for rejecting noisy input signals.
It is yet another advantage of the present invention to provide an input circuit that automatically turns on and off the trip point depending on the input voltage standard.
It is yet another advantage of the present invention to provide an input circuit that can be configured via a single configuration bit.